1. Field of the Invention
The present invention relates to a method for fabricating an embedded static random access memory, and more particularly, to a method for fabricating an embedded static random access memory with improved random single bit failure rate.
2. Description of the Prior Art
An embedded static random access memory (SRAM) comprises a logic circuit and a static random access memory connected to the logic circuit. SRAM is a kind of volatile memory cell, which means it preserves data only while power is continuously applied. SRAM is built of cross-coupled inverters that store data during the time that power remains applied, unlike dynamic random access memory (DRAM) that needs to be periodically refreshed. Because of its high access speed, SRAM is also used in computer system as a cache memory.
Please refer to FIG. 1, which shows a circuit diagram of typical six-transistors SRAM (6T-SRAM) 10. The 6T-SRAM cell 10 comprises pull-up transistors 12 and 14, pull-down transistors 16 and 18, and access transistors 20 and 22. These six transistors constitute a set of flip-flops. Pull-up transistors 12, 14 and pull-down transistors 16, 18 constitute a latch that stores data in the storage node 24, 26. Because the pull-up transistors 12, 14 act as power load devices they can be replaced by resistors. At this point, the static random access memory is a four-transistors SRAM (4T-SRAM).
Generally speaking, the pull-up transistors 12, 14 of the 6T-SRAM cell 10 comprise P-type metal oxide semiconductor (PMOS) transistors. The pull-down transistors 16, 18 and the access transistors 20, 22 comprise N-type metal oxide semiconductor (NMOS) transistor. The pull-up transistor 12 and the pull-down transistor 16 constitute a series circuit 28. One end of the series circuit 28 is connected to a power supply 32 and the other end of the series circuit 28 is connected to a ground 34. Equally, the pull-up transistor 14 and the pull-down transistor 18 constitute a series circuit 30. One end of the series circuit 30 is connected to the power supply 32 and the other end of the series circuit 30 is connected to the ground 34.
Additionally, the storage node 24 is connected to the respective gates of the pull-down transistor 18 and the pull-up transistor 14. The storage node 24 is also connected to the drains of the pull-down transistor 16, pull-up transistor 12 and the access transistor 20. Equally, the storage node 26 is connected to the respective gates of the pull-down transistor 16 and the pull-up transistor 12. The storage node 26 is also connected to the drains of the pull-down transistor 18, pull-up transistor 14 and the access transistor 22. The gates of the access transistors 20 and 22 are respectively coupled to a word line 36, and the sources are coupled to a relative data line 38.
The aggressive scaling of MOS transistors faces severe challenges to the effective capacitance, which is usually expressed as dielectric inversion thickness (Tox_INV). When a gate dielectric layer is in an inversion condition, the gate possesses less carrier mobility than metal materials, thus causing lower effective capacitance. There are two primary methods for improving the effective capacitance. One is to improve the property of the gate dielectric layer, such as using high-K materials or decreasing the thickness of the gate dielectric layer. The other one is to decrease the depletion region of the gate, such as doping atoms or implanting ions on the polysilicon gate to improve the carrier mobility.
U.S. Patent No. 2003/0032231 A1, paragraphs 38 and 47, teaches a most common method used in industry to effectively decrease the Tox_INV by providing a N+ polysilicon doping process to the N type polysilicon of NMOS devices.
Please refer to FIG. 2, which illustrates a schematic plan view of an embedded static random access memory. As shown in FIG. 2, a semiconductor substrate 40 is provided. A memory cell area 42 and a logic area 44 are defined on the semiconductor substrate 40. According to different designs and functional desires for the electrical circuits, a plurality of active areas 46, N wells 48 and P wells 50 are formed respectively in the memory cell area 42 and the logic area 44 of the semiconductor substrate 40.
A patterned silicon layer 52 is deposited on the N well 48, the P well 50 and the active area 46. At this point, a 6T-SRAM cell 60 is defined in the memory cell area 42, and a logic device 80, which comprises a complementary metal oxide semiconductor (CMOS), is defined in the logic area 44.
As shown in FIG. 2, the 6T-SRAM cell 60 comprises pull-up transistor 62, 64, pull-down transistors 66, 68, and access transistors 70, 72. The pull-up transistor 62 and the pull-down transistor 66 comprise a common gate 74. The pull-up transistor 64 and the pull-down transistor 68 comprise a common gate 76. The access transistors 70 and 72 comprise a common gate 78. Additionally, the logic device 80 in the logic area 44 comprises a PMOS transistor 82 with a gate 86 and an NMOS transistor 84 with a gate 88.
When the method disclosed in U.S. Patent No. 2003/0032231 A1 is performed to reduce the gate depletion region, the gate formed on the P well 50 is doped with N+ dopant. It should be noted that the pull-up transistor 62 and the pull-down transistor 66 comprise a common gate 74, and the pull-up transistor 64 and the pull-down transistor 68 comprise a common gate 76. The portion of the common gates 74 and 76 located on the P well 50 are the gates (which belong to the pull-down transistors 66 and 68) doped with N+ dopant. Equally, the portion of the common gates 74 and 76 located on the N well are the gates (which belong to the pull-up transistors 62 and 64) are the gates doped with no N+ dopant.
In an ideal condition, the symmetrical common gates 74 and 76 belonging to the pull-down transistors 66 and 68 respectively have the same N+ dosage. According to some manufacturing or non-manufacturing factors such as the misalignment of the active area, the deviation of the critical dimension of gates, the shift of the mask for the N+ polysilicon doping process, however, the symmetrical common gates 74 and 76 usually possess unsymmetrical N+ dosage. This unsymmetrical dosage causes increasing deviations of the relative saturated current of the drain regions in the pull-up transistors 62 and 64. The current deviation induces the failure to the memory cell, namely the bit data stored in this memory cell fail. Thereby, N+ polysilicon doping process can reduce the Tox_INV, but it also increases the random single bit (RSB) failure rate in the memory array.
It would thus be highly desirable to provide a method for fabricating an embedded SRAM with improved RSB failure rate.